1. Introduction

  Semiconductor industry dominated by silicon is nearing the limits of the performance improvements. Therefore, research on novel and nontraditional materials for future semiconductor devices is necessary. Recently, graphene, a one-atom-thick sp2–bonded carbon planar sheet, has gained much attention due to its unique physical properties since isolated graphene sheets were actually found by mechanical exfoliation in 2004. It has been proposed as a potential material for various electronic applications such as flexible transparent electrodes, logic devices, high frequency transistors, and memory devices. These result from merits of carries in graphene, including high mobility (> 105 cm2∙V-1∙s-1), high saturation velocity (~ 5.5×107 cm∙s-1), stable crystal structure, ultrathin layer thickness (~ 0.4 nm), etc..

 

 

2. Fabrication of graphene field-effect transistors

  To fabricate graphene-based devices through existing process technology being used in the semiconductor industry, it is essential to synthesize large-area graphene films. Various methods have been developed for this, but it is well known that LPCVD (Low pressure chemical vapor deposition) technology is the most useful method for large-area synthesis of graphene films. Using LPCVD, graphene films can be grown on several transition metals which are used as catalysts for decomposition of precursor materials and provide a geometrical fit for growth of graphene. After synthesis of graphene films, the films were transferred onto SiO2/Si wafer to evaluate quality or uniformity of the films using optical microscopy, Raman spectroscopy, and atomic force microscope (AFM).

 

 

Reaction time

The flow rate of CH4

30 sccm

40 sccm

50 sccm

20 min

Single-layer

graphene islands

(not fully covered)

Single-layer

graphene film

Single-layer

graphene film

30 min

Single-layer

graphene islands

(not fully covered)

Bi-layer graphene islands on  Single-layer graphene film

Multi-layer

graphene film

40 min

Multi-layer

graphene film

Multi-layer

graphene film

Bi-layer graphene islands on  Single-layer graphene film

 

 

 

 

 

 

 

 

 

 

 

 

3. Properties of graphene field-effect transistors

  A schematic of a typical top-gated graphene field-effect device can be seen below the text. The device consists of a graphene layer sandwiched between SiO2 layers that serve as gate insulators for the back-gate and the top-gate. The graphene layer is equipped with metallic source and drain contacts.

  The graph below is conductance of a single layer graphene used as the channel of a field effect transistor, as a function of the top-gate bias voltage at different back-gate voltages. This shows an ambipolar characteristic of conductance.

 

 

References

1) A. K. Geim, and K. S. Novoselov: Nat. Mater. 6 (2007) 183.

2) K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov: Science 306 (2004) 666.

3) Richard Van Noorden: nature 469 (2011) 15

4) M. Baus, T.J. Echtermeyer, B.N. Szafranek, M.C. Lemme, “Device Architectures based on Grapheneb Channels”

5) Phaedon Avouris, “Graphene: Electronic and Photonic Properties and Devices”