1. Introduction

  Strain technology has taken an important role to improve CMOSFET devices lately. It is reported that tensile mechanical stress on NMOS and compressive stress on PMOS increase carrier mobility and current drivability. Moreover, since it is achievable just by adding a process that applies mechanical stress into the existing CMOS technology process flow, the strain technology is highly compatible and scalable.Recently, amorphous oxide semiconductors (AOSs) have attracted considerable attention as novel candidates for channel materials of thin-film transistors (TFTs). Compared to traditional amorphous semiconductors such as a-Si and organic TFT materials, AOS based TFTs have clearly superior performances because of their unique features (high performance, low process temperature, and transparency).

Fig. 1. Strained-Si compatible with typical CMOS process flow

 

2. Strain Technology with HV-MOSFET

  Since a high-voltage MOSFET requires characteristics such as current drivability, high transconductance, and low on-resistance, strain technology is expected to yield positive results when it is applied on high-voltage MOSFETs. A high-voltage MOSFET as a power device has its merits in high switching power and low on-resistance characteristic. However, a low transconductance, small signal output resistance, and small threshold voltage, which are the results of a hot electron effect due to the large lateral electric field, are the drawbacks of the device. Strain technology can be applied to enhance it.

Fig. 2. Strained-Si channel high-voltage NMOSFET shows better transconductance characteristic than its Conventional-Si channel counterpart

 

  However, the drawbacks which come with mechanical stress like lower breakdown voltage, low subthreshold slope, and increased junction leakage at off state current deteriorate the device performance. Unlike tensile stress which decreases off-leakage current, compressive stress for PMOS increases off-leakage current. Also, it has been discovered that breakdown voltage and subthreshold slope decreases when it comes to high voltage operations.

Fig. 3. The breakdonwn voltage characteristics of the Strained-Si HVNMOS compared with the Conventional-Si HVNMOS

 

3. Our research

  In this research, we will look into the effects of the strain technology on High-voltage MOSFET in terms of advantages and drawbacks. We will study the characteristics of a high-voltage MOSFET. Then, the benefits of the strain technology when it is applied on a high-voltage MOSFET will be investigated. The downside effects due to the mechanical stress on a high-voltage MOSFET will be surveyed. Finally, we will look for the methods which maximize the advantages and minimize the drawbacks of the strained high-voltage MOSFETs.

  For this goal, a TCAD simulation and various sample measurement will be implemented. Sentaurus made by Synopsys will be used as the TCAD simulation tool. TEG chips will be measured to propose improvements of the devices. u-Raman spectroscopy will be implemented to evaluate mechanical stress and strain profile of TSV structure, revealing the relationship between the TSV structure diameter and the stress applied. The stress profile vibration will be also observed for certain temperature cycles. Moreover, the defects caused from following processes could be analyzed with Pohang Light Source.